FUJITSU F2MCTM-16LX - Manual (Page 458)

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CHAPTER 20 LIN-UART
predefined value.
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Bus idle function
The bus idle function cannot be used in synchronous mode 2.
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AD bit (serial control register (SCR): address/data type select bit)
Special care has to be taken when using the AD bit (Address-Data-Bit for multiprocessor mode 1) of the
Serial Control Register. This bit is both a control and a flag bit, because writing to it sets the AD bit for
transmission, whereas reading from it returns the last received AD bit. Internally, the received and the
transmitted value are stored in different registers, but in Read-Modify-Write instructions, the transmitted
value is read. This can lead to a wrong value in the AD bit, when one of the other bits in the same register
is accessed by an instruction of this kind.
Therefore, this bit should be written by the last register access before transmission. Alternatively, using
byte wise access and writing the correct values for all bits at once avoids this problem.
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Software reset of LIN-UART
Perform the software reset (SMR: UPCL=1), when the TXE bit of the SCR register is "0".
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LIN Synch detection
In mode 3 (LIN operation), the LBD bit in the ESCR register is set to "1" if the input signal is kept at "0"
for more than equal to 11-bit time. Then the LIN-UART waits for the following synch field to be received.
If the LIN-UART is set into this state for other reasons than the synch break, it recognizes that synch break
is inputted (LBD = 1) and waits for synch field.
In this case, execute the LIN-UART reset (SMR: UPCL = 1).