FUJITSU F2MCTM-16LX - Manual (Page 423)

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CHAPTER 20 LIN-UART
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Reception Interrupt
If one of the following events occurs in reception mode, the corresponding flag bit of the serial status
register (SSR) is set to "1":
• Data reception is completed, i. e. the received data was transferred from the serial input shift register to
the reception data register (RDR) and data can be read: RDRF
• Overrun error, i. e. RDRF = 1 and RDR was not read by the CPU and next serial data is received: ORE
• Framing error, i. e. a stop bit was expected, but a "0"-bit was received: FRE
• Parity error, i. e. a wrong parity bit was detected: PE
If at least one of these flag bits above go "1" and the reception interrupt is enabled (SSR: RIE = 1), a
reception interrupt request is generated.
If the reception data register (RDR) is read, the RDRF flag is automatically cleared to "0". The error flags
are cleared to "0", if a "1" is written to the clear reception error (CRE) flag bit of the serial control register
(SCR).
Note:
The CRE flag is "write only" and by writing a "1" to it, it is internally held to "1" for one clock cycle.
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Transmission Interrupt
If transmission data is transferred from the transmission data register (TDR) to the transfer shift register
and transfer is started, the transmission data empty flag bit (TDRE) of the serial status register (SSR) is set
to "1". In this case an interrupt request is generated, if the transmission interrupt enable (TIE) bit of the
SSR was set to "1" before.
Note:
The initial value of TDRE (after hardware or software reset) is "1". So an interrupt is generated
immediately then, if the TIE flag is set to "1". Also note, that the only way to reset the TDRE flag is
writing data to the transmission data register (TDR).
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LIN Synchronization Break Interrupt
This paragraph is only relevant, if LIN-UART operates in mode 3 as a LIN slave.
If the bus (serial input) goes "0" (dominant) for more than 11 bit times, the LIN synch break detected
(LBD) flag bit of the extended status/control register (ESCR) is set to "1". Note, that in this case after 9 bit
times the reception error flags are set to "1", therefore the RXE flag has to set to "0", if only a LIN synch
break detect is desired.
The LIN synch break interrupt and the LBD flag are cleared after writing a "0" to the LBD flag. The LBD
flag has to be performed before input capture interrupt for LIN synch field.
When LIN synch break detection is performed, it is necessary to disable the reception (SCR: RXE=0).