FUJITSU F2MCTM-16LX - Manual (Page 672)

656
INDEX
Sector Configuration of the 512K-bit Flash Memory
.......................................................... 531
Setting the Flash Memory to the Read/reset State
.......................................................... 545
Writing Data to the Flash Memory ..................... 546
Writing to the Flash Memory ............................. 546
Writing to/erasing Flash Memory ....................... 530
Flash Memory Control Status Register
Flash Memory Control Status Register (FMCS)
.................................................. 530, 535
Flash Memory Mode
Flash Memory Mode ........................................ 533
Flash Memory Write
Detailed Explanation of Flash Memory Write/erase
.......................................................... 544
Flash Microcomputer Programmer
Example of Minimum Connection to Flash
Microcomputer Programmer
(Power supplied from programmer)
....... 563
Example of Minimum Connection to Flash
microcontroller Programmer ................ 561
Flash Security
Behavior Under the Flash Security Feature ......... 551
How to Disable the Flash Security Feature .......... 551
How to Enable the Flash Security Feature ........... 551
FMCS
Flash Memory Control Status Register (FMCS)
.................................................. 530, 535
Frame Format
Setting Frame Format ....................................... 494
Free-run Timer
Block Diagram of 16-bit Free-run Timer ............ 213
Explanation of Operation of 16-bit Free-run Timer
.......................................................... 229
H
HALT
Conditions for Canceling Bus Operation Stop
(HALT=0) .......................................... 457
Conditions for Setting Bus Operation Stop (HALT=1)
.......................................................... 457
State during Bus Operation Stop (HALT=1) ....... 457
Hardware Interrupt
Hardware Interrupt Operation .............................. 68
Hardware Interrupts ...................................... 56, 67
Occurrence and Release of Hardware Interrupt ...... 69
Structure of Hardware Interrupt ........................... 67
Hardware Sequence Flags
Hardware Sequence Flags ................................. 539
I
I/O Area
I/O Area ............................................................ 30
I/O Maps
I/O Maps (00XX Addresses) ............................. 568
I/O Pins
Status of I/O Pins (Single-chip Mode) ................ 156
I/O Port
I/O Port Registers ............................................ 169
I/O Ports ......................................................... 168
I/O Timer
16-bit I/O Timer Interrupt and EI
2
OS ................. 228
Block Diagram of 16-bit I/O Timer .................... 211
Functions of 16-bit I/O Timer ........................... 210
Generation of Interrupt Request from 16-bit I/O Timer
......................................................... 216
Interrupts of 16-bit I/O Timer ............................ 227
Module Configuration of 16-bit I/O Timer ......... 210
Pins of 16-bit I/O Timer ................................... 216
Precautions when Using 16-bit I/O Timer ........... 233
Program Example of 16-bit I/O Timer ................ 234
ICE
Input Capture Edge Register (ICE) .................... 224
ICR
Interrupt Control Register (ICR) .......................... 61
ICS
Input Capture Control Status Registers (ICS01,ICS23)
......................................................... 221
ID
Setting ID ........................................................ 494
ID Registers
List of Message Buffers (ID registers) ................ 448
ILSR
Input Level Select Register (ILSR) .................... 176
Indirect Addressing
Indirect Addressing .......................................... 586
Initialized State
Operating Mode in Initialized State ................... 115
Input Capture
Block Diagram of Input Capture ........................ 214
Setting of Input Capture .................................... 231
Input Capture Control Status Registers
Input Capture Control Status Registers (ICS01,ICS23)
......................................................... 221
Input Capture Edge Register
Input Capture Edge Register (ICE) .................... 224
Input Capture Register
Input Capture Register (IPCP) ........................... 223
Input Level Select Register
Input Level Select Register (ILSR) .................... 176
Input-output Circuits
Input-output Circuits .......................................... 17
Instruction
Exception due to Execution of an Undefined
Instruction ........................................... 82
Execution of an Undefined Instruction ................. 82
Interrupt Disable Instructions .............................. 51