FUJITSU F2MCTM-16LX - Manual (Page 525)

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CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.3.1 Address Detection Control Register (PACSR0/PACSR1)
The address detection control register enables or disables output of an interrupt at an
address match. When an address match is detected when output of an interrupt at an
address match is enabled, the INT9 interrupt is generated.
■ Address Detection Control Register 0 (PACSR0)
Figure 22.3-2 Address Detection Control Register 0 (PACSR0)
4 5 3 2 1 0 7 6
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 9 E H 0 0 0 0 0 0 0 0 B AD2E AD1E AD0E
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
Address Reset value
bit 0
Reserved Reserved bit
0 Always set to "0"
bit 1
AD0E Address match detection enable bit 0
0 Disables address match detection in PADR0
1 Enables address match detection in PADR0
bit 2
Reserved Reserved bit
0 Always set to "0"
bit 5
AD2E Address match detection enable bit 2
0 Disables address match detection in PADR2
1 Enables address match detection in PADR2
bit 4
Reserved Reserved bit
0 Always set to "0"
bit 3
AD1E Address match detection enable bit 1
0 Disables address match detection in PADR1
1 Enables address match detection in PADR1
bit 6
Reserved Reserved bit
0 Always set to "0"
bit 7
Reserved Reserved bit
0 Always set to "0"
R/W : Read/Write
: Reset value