FUJITSU F2MCTM-16LX - Manual (Page 223)

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CHAPTER 12 WATCHDOG TIMER
12.5 Precautions when Using Watchdog Timer
Take the following precautions when using the watchdog timer.
■ Precautions when Using Watchdog Timer
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Stopping watchdog timer
The watchdog timer is stopped by all the reset sources.
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Interval time
• The interval time uses the carry signal of the timebase timer or watch timer as a count clock. If the
timebase timer or watch timer is cleared, the interval time of the watchdog timer may become long.
Note that the timebase timer is cleared when "0" is written to the timebase timer counter clear bit (TBR)
in the timebase timer control register (TBTC) and when the clock mode changes from the main clock to
PLL clock, from the subclock to main clock, or from the subclock to PLL clock.
• Set the interval time concurrently when starting the watchdog timer. Setting the time interval except
starting the watchdog timer is ignored.
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Precautions when creating program
When clearing the watchdog timer repeatedly in the main loop, set a shorter processing time for the main
loop, including interrupt processing, than the interval time of watchdog timer.
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Precautions in subclock mode
In the subclock mode, be sure to set the watchdog clock select bit (WDCS) in the watch timer control
register (WTC) to "0" and select the output of the watch timer.