FUJITSU F2MCTM-16LX - Manual (Page 491)

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21.4.19 Receive Overrun Register (ROVRR)
If RCx of the reception complete register (RCR) is 1 when completing storing of a
received message in the message buffer (x), ROVRx becomes 1, indicating that
reception has overrun.
■ Register Configuration
Figure 21.4-19 Configuration of the Receive overrun Register (ROVRR)
■ Register Function
Writing 0 to ROVRx results in ROVRx = 0. Writing 1 to ROVRx is ignored. After checking that reception
has overrun, write 0 to ROVRx to set it to 0.
1 is read when a Read-Modify-Write instruction is performed.
Note:
If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same
time, the bit is set to 1.
Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ROVRR1(Upper)
CAN1: 00008D H RVOR15 RVOR14 RVOR13 RVOR12 RVOR11 RVOR10 RVOR9 RVOR8 Reset value
0 0 0 0 0 0 0 0
B
R/W R/W R/W R/W R/W R/W R/W R/W
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ROVRR1(Lower)
CAN1: 00008C H RVOR7 RVOR6 RVOR5 RVOR4 RVOR3 RVOR2 RVOR1 RVOR0 Reset value
0 0 0 0 0 0 0 0
B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write