FUJITSU F2MCTM-16LX - Manual (Page 377)

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CHAPTER 18 8-/10-BIT A/D CONVERTER
■ Operation of Single-shot Conversion Mode
• When the start trigger is inputted, A/D conversion starts from the channel set by the A/D conversion
start channel select bits (ANS3 to ANS0) and is performed continuously up to the channel set by the A/
D conversion end channel select bits (ANE3 to ANE0).
• The A/D conversion stops at the termination of the A/D conversion for the channel set by the A/D
conversion end channel select bits (ANE3 to ANE0).
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control
status register (ADCS:BUSY).
• When the A/D conversion mode select bits (MD1, MD0) are set to "00
B
", this mode can be restarted
during A/D conversion. If the bits are set to "01
B
", this mode cannot be restarted during A/D
conversion.
[When start and end channels are the same]
If the start and end channels have the same channel number (ADCS: ANS3 to ANS0=ADCS: ANE3 to
ANE0), only one A/D conversion for one channel set as the start channel (= end channel) is performed and
terminated.
[Conversion order in single-shot conversion mode]
Table 18.5-1 gives an example of the conversion order in the single-shot conversion mode.
Table 18.5-1 Conversion Order in Single-shot Conversion Mode
Start Channel End Channel Conversion Order
AN0 pin
(ADCS: ANS="0000
B
")
AN3 pin
(ADCS: ANE="0011
B
")
AN0
→ AN1 → AN2 → AN3 → end
AN3 pin
(ADCS: ANS="0011
B
")
AN3 pin
(ADCS: ANE="0011
B
")
AN3
→ end