FUJITSU F2MCTM-16LX - Manual (Page 310)

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CHAPTER 16 8-/16-BIT PPG TIMER
16.3.2 PPGD Operation Mode Control Register (PPGCD)
The PPGD operation mode control register provides the following settings about
operation of 8-/16-bit PPG timer D:
• Enabling or disabling operation of 8-/16-bit PPG timer D
• Switching between pin functions (enabling or disabling pulse output)
• Enabling or disabling underflow interrupt
• Setting underflow interrupt request flag
• Setting the operation mode of the 8-/16-bit PPG timer D and C
This section explains the PPGCD function only. The PPGCF has the same function as
the PPGCD, and the 8-/16-bit PPG timer F is set.
■ PPGD Operation Mode Control Register (PPGCD)
Figure 16.3-3 PPGD Operation Mode Control Register (PPGCD)
12 13 11 10 9 8 15 14
− R/W R/W R/W R/W R/W R/W
0 X 0 0 0 0 0 1 B
W
PEN1 PE1 PIE1
Re-
served
PUF1 MD1 MD0
Address:
chD PPGCD 000049
H
Other channel:
chF
PPGCF 00004D
H
Reset value
bit 8
Re-
served
Reserved bit
1 Always set to "1".
bit 10 bit 9
MD1 MD0 Operation mode select bits
0 0
8-bit PPG output 2 channels
independent operation mode
0 1
8+8-bit PPG output operation
mode
1 0 Setting disable
1 1 16-bit PPG output operation mode
bit 11
PUF1
Underflow generation flag bit
Read Write
0 No underflow Clears PUF1 bit
1 Underflow No effect
bit 12
PIE1 Underflow interrupt enable bit
0 Underflow interrupt request disable
1 Underflow interrupt request enable
bit 13
PE1 PPG1 pin output enable bit
0
General-purpose I/O port (pulse output
disable)
1 PPG1 output (pulse output enable)
bit 15
PEN1 PPG1 operation enable bit
0 Counting disable (holds "L" level output)
1 Counting enable
R/W : Read/Write
W : Write only
X : Indeterminate
− : Undefined
: Reset value