FUJITSU F2MCTM-16LX User Manual
16lx
Table of contents
Document Outline
- CHAPTER 1 OVERVIEW
- CHAPTER 2 CPU
- CHAPTER 3 INTERRUPTS
- CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE
- 4.1 Overview of Delayed Interrupt Generation Module
- 4.2 Block Diagram of Delayed Interrupt Generation Module
- 4.3 Configuration of Delayed Interrupt Generation Module
- 4.4 Explanation of Operation of Delayed Interrupt Generation Module
- 4.5 Precautions when Using Delayed Interrupt Generation Module
- 4.6 Program Example of Delayed Interrupt Generation Module
- CHAPTER 5 CLOCKS
- CHAPTER 6 CLOCK SUPERVISOR
- CHAPTER 7 RESETS
- CHAPTER 8 LOW-POWER CONSUMPTION MODE
- 8.1 Overview of Low-Power Consumption Mode
- 8.2 Block Diagram of the Low-Power Consumption Control Circuit
- 8.3 Low-Power Consumption Mode Control Register (LPMCR)
- 8.4 CPU Intermittent Operation Mode
- 8.5 Standby Mode
- 8.6 Status Change Diagram
- 8.7 Status of Pins in Standby Mode and during Hold and Reset
- 8.8 Usage Notes on Low-Power Consumption Mode
- CHAPTER 9 MEMORY ACCESS MODES
- CHAPTER 10 I/O PORTS
- CHAPTER 11 TIMEBASE TIMER
- CHAPTER 12 WATCHDOG TIMER
- CHAPTER 13 16-Bit I/O TIMER
- 13.1 Overview of 16-bit I/O Timer
- 13.2 Block Diagram of 16-bit I/O Timer
- 13.3 Configuration of 16-bit I/O Timer
- 13.4 Interrupts of 16-bit I/O Timer
- 13.5 Explanation of Operation of 16-bit Free-run Timer
- 13.6 Explanation of Operation of Input Capture
- 13.7 Precautions when Using 16-bit I/O Timer
- 13.8 Program Example of 16-bit I/O Timer
- CHAPTER 14 16-BIT RELOAD TIMER
- 14.1 Overview of the 16-bit Reload Timer
- 14.2 Block Diagram of 16-bit Reload Timer
- 14.3 Configuration of 16-bit Reload Timer
- 14.4 Interrupts of 16-bit Reload Timer
- 14.5 Explanation of Operation of 16-bit Reload Timer
- 14.6 Precautions when Using 16-bit Reload Timer
- 14.7 Sample Program of 16-bit Reload Timer
- CHAPTER 15 WATCH TIMER
- CHAPTER 16 8-/16-BIT PPG TIMER
- CHAPTER 17 DTP/EXTERNAL INTERRUPTS
- CHAPTER 18 8-/10-BIT A/D CONVERTER
- CHAPTER 19 LOW VOLTAGE DETECTION/ CPU OPERATING DETECTION RESET
- 19.1 Overview of Low Voltage/CPU Operating Detection Reset Circuit
- 19.2 Configuration of Low Voltage/CPU Operating Detection Reset Circuit
- 19.3 Low Voltage/CPU Operating Detection Reset Circuit Register
- 19.4 Operating of Low Voltage/CPU Operating Detection Reset Circuit
- 19.5 Notes on Using Low Voltage/CPU Operating Detection Reset Circuit
- 19.6 Sample Program for Low Voltage/CPU Operating Detection Reset Circuit
- CHAPTER 20 LIN-UART
- 20.1 Overview of LIN-UART
- 20.2 Configuration of LIN-UART
- 20.3 LIN-UART Pins
- 20.4 LIN-UART Registers
- 20.4.1 Serial Control Register (SCR)
- 20.4.2 LIN-UART Serial Mode Register (SMR)
- 20.4.3 Serial Status Register (SSR)
- 20.4.4 Reception and Transmission Data Register (RDR/TDR)
- 20.4.5 Extended Status/Control Register (ESCR)
- 20.4.6 Extended Communication Control Register (ECCR)
- 20.4.7 Baud Rate Generator Register 0 and 1 (BGR0/1)
- 20.5 LIN-UART Interrupts
- 20.6 LIN-UART Baud Rates
- 20.7 Operation of LIN-UART
- 20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1)
- 20.7.2 Operation in Synchronous Mode (Operation Mode 2)
- 20.7.3 Operation with LIN Function (Operation Mode 3)
- 20.7.4 Direct Access to Serial Pins
- 20.7.5 Bidirectional Communication Function (Normal Mode)
- 20.7.6 Master-Slave Communication Function (Multiprocessor Mode)
- 20.7.7 LIN Communication Function
- 20.7.8 Sample Flowcharts for LIN-UART in LIN communication (Operation Mode 3)
- 20.8 Notes on Using LIN-UART
- CHAPTER 21 CAN CONTROLLER
- 21.1 Features of CAN Controller
- 21.2 Block Diagram of CAN Controller
- 21.3 List of Overall Control Registers
- 21.4 Classifying CAN Controller Registers
- 21.4.1 Configuration of Control Status Register (CSR)
- 21.4.2 Function of Control Status Register (CSR)
- 21.4.3 Correspondence between Node Status Bit and Node Status
- 21.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1)
- 21.4.5 Last Event Indicator Register (LEIR)
- 21.4.6 Receive and Transmit Error Counters (RTEC)
- 21.4.7 Bit Timing Register (BTR)
- 21.4.8 Prescaler Setting by Bit Timing Register (BTR)
- 21.4.9 Message Buffer Valid Register (BVALR)
- 21.4.10 IDE Register (IDER)
- 21.4.11 Transmission Request Register (TREQR)
- 21.4.12 Transmission RTR Register (TRTRR)
- 21.4.13 Remote Frame Receiving Wait Register (RFWTR)
- 21.4.14 Transmission Cancel Register (TCANR)
- 21.4.15 Transmission Complete Register (TCR)
- 21.4.16 Transmission Interrupt Enable Register (TIER)
- 21.4.17 Reception Complete Register (RCR)
- 21.4.18 Remote Request Receiving Register (RRTRR)
- 21.4.19 Receive Overrun Register (ROVRR)
- 21.4.20 Reception Interrupt Enable Register (RIER)
- 21.4.21 Acceptance Mask Select Register (AMSR)
- 21.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
- 21.4.23 Message Buffers
- 21.4.24 ID Register x (x = 0 to 15) (IDRx)
- 21.4.25 DLC Register x (x = 0 to 15) (DLCRx)
- 21.4.26 Data Register x (x = 0 to 15) (DTRx)
- 21.5 Transmission of CAN Controller
- 21.6 Reception of CAN Controller
- 21.7 Reception Flowchart of CAN Controller
- 21.8 How to Use CAN Controller
- 21.9 Procedure for Transmission by Message Buffer (x)
- 21.10 Procedure for Reception by Message Buffer (x)
- 21.11 Setting Configuration of Multi-level Message Buffer
- 21.12 Setting the CAN Direct Mode Register
- 21.13 Precautions when Using CAN Controller
- CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
- CHAPTER 23 ROM MIRRORING MODULE
- CHAPTER 24 512K-BIT FLASH MEMORY
- 24.1 Overview of 512K-bit Flash Memory
- 24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory
- 24.3 Write/Erase Modes
- 24.4 Flash Memory Control Status Register (FMCS)
- 24.5 Starting the Flash Memory Automatic Algorithm
- 24.6 Confirming the Automatic Algorithm Execution State
- 24.7 Detailed Explanation of Writing to and Erasing Flash Memory
- 24.8 Notes on Using 512K-bit Flash Memory
- 24.9 Flash Security Feature
- CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION
- 25.1 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S)
- 25.2 Example of Serial Programming Connection (User Power Supply Used)
- 25.3 Example of Serial Programming Connection (Power Supplied from Programmer)
- 25.4 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used)
- 25.5 Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer)
- CHAPTER 26 ROM SECURITY FUNCTION
- APPENDIX