FUJITSU F2MCTM-16LX - Manual (Page 322)

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CHAPTER 16 8-/16-BIT PPG TIMER
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Output waveform in 16-bit PPG output operation mode
The High and Low pulse widths to be outputted are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle. For example, if the value in the PPG reload register is
"0000
H
", the pulse width has one count clock cycle, and if the value is "FFFF
H
", the pulse width has 65,536
count clock cycles.
The equations for calculating the pulse width are shown below:
PL=T
× (L+1)
PH=T
× (H+1)
PL: Low width of output pulse
PH: High width of output pulse
L: Values of 16 bits in PPG reload register (PRLLn+PRLLm)
H: Values of 16 bits in PPG reload register (PRLHn+PRLHm)
T: Count clock cycle
Figure 16.5-5 shows the output waveform in the 16-bit PPG output operation mode.
Figure 16.5-5 Output Waveform in 16-bit PPG Output Operation Mode
T × (L + 1) T
×
(H
+
1)
Operation start Operation stop
PPG operation enable
bit (PEN)
PPG output pin
L : Values of 16 bits in PPG reload register (PRLLm + PRLLn)
H : Values of 16 bits in PPG reload register (PRLHm + PRLHn)
T : Count clock cycle
Note: n = C, E
m = n + 1