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6 reception of can controller, Reception of can controller, Er (see "21.6 reception of – FUJITSU F2MCTM-16LX User Manual

Page 506: Can controller")

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CHAPTER 21 CAN CONTROLLER

21.6

Reception of CAN Controller

Reception starts when the start of data frame or remote frame (SOF) is detected on the
CAN bus.

Acceptance Filtering

The received message in the standard frame format is compared with the message buffer (x) set in the

standard frame format (IDEx of the IDE register (IDER) is 0). The received message in the extended frame

format is compared with the message buffer (x) set (IDEx is 1) in the extended frame format.

If all the bits set to Compare by the acceptance mask agree after comparison between the received message

ID and acceptance code (ID register (IDRx) for comparing with the received message ID), the received

message passes to the acceptance filter of the message buffer (x).

Storing Received Message

When the receive operation is successful, received messages are stored in a message buffer x including IDs

passed through the acceptance filter.

When receiving data frames, received messages are stored in the ID register (IDRx), DLC register

(DLCRx), and data register (DTRx).

Even if received message data is less than 8 bytes, some data is stored in the remaining bytes of the DTRx

and its value is undefined.

When receiving remote frames, received messages are stored only in the IDRx and DLCRx, and the DTRx

remains unchanged.

If there is more than 1 message buffer including IDs passed through the acceptance filter, the message

buffer x in which received messages are to be stored is determined according to the following rules.

The order of priority of the message buffer x (x = 0 to 15) rises as its number lower; in other words,

message buffer 0 is given the highest and the message buffer 15 is given the lowest priority.

Basically, message buffers with the RCx bit of 0 in the receive completion register (RCR) are preferred

in storing received messages.

If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare (for message

buffers with the AMSx.1 and AMSx.0 bits set to 00

B

), received messages are stored irrespective of the

value of the RCx bit of the RCR.

If there are message buffers with the RCx bit of the RCR set to 0, or with the bits of the AMSR set to

All Bits Compare, received messages are stored in the lowest-number (highest-priority) message buffer

x.

If there are no message buffers above-mentioned, received messages are stored in a lower-number

message buffer x.

Message buffers should be arranged in ascending numeric order. The lowest message buffers should be

with All Bits Compare, then AMR0 or AMR1 masks. And The highest message buffers should be with

All Bits Mask.