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21.4.20 Reception Interrupt Enable Register (RIER) ............................................................................. 476
21.4.21 Acceptance Mask Select Register (AMSR) ............................................................................... 477
21.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) .......................................................... 479
21.4.23 Message Buffers ........................................................................................................................ 481
21.4.24 ID Register x (x = 0 to 15) (IDRx) .............................................................................................. 483
21.4.25 DLC Register x (x = 0 to 15) (DLCRx) ....................................................................................... 485
21.4.26 Data Register x (x = 0 to 15) (DTRx) ......................................................................................... 486
21.5
Transmission of CAN Controller ..................................................................................................... 488
21.6
Reception of CAN Controller .......................................................................................................... 490
21.7
Reception Flowchart of CAN Controller .......................................................................................... 493
21.8
How to Use CAN Controller ............................................................................................................ 494
21.9
Procedure for Transmission by Message Buffer (x) ....................................................................... 496
21.10 Procedure for Reception by Message Buffer (x) ............................................................................. 498
21.11 Setting Configuration of Multi-level Message Buffer ....................................................................... 500
21.12 Setting the CAN Direct Mode Register ........................................................................................... 502
21.13 Precautions when Using CAN Controller ........................................................................................ 503
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ......................................... 505
22.1
Overview of Address Match Detection Function ............................................................................. 506
22.2
Block Diagram of Address Match Detection Function .................................................................... 507
22.3
Configuration of Address Match Detection Function ...................................................................... 508
22.3.1
Address Detection Control Register (PACSR0/PACSR1) ......................................................... 509
22.3.2
Detect Address Setting Registers (PADR0 to PADR5) ............................................................. 513
22.4
Explanation of Operation of Address Match Detection Function .................................................... 516
22.4.1
Example of using Address Match Detection Function ............................................................... 517
22.5
Program Example of Address Match Detection Function ............................................................... 522
CHAPTER 23 ROM MIRRORING MODULE ................................................................... 525
23.1
Overview of ROM Mirroring Function Select Module ...................................................................... 526
23.2
ROM Mirroring Function Select Register (ROMM) ......................................................................... 528
CHAPTER 24 512K-BIT FLASH MEMORY .................................................................... 529
24.1
Overview of 512K-bit Flash Memory ............................................................................................... 530
24.2
Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory .......... 531
24.3
Write/Erase Modes ......................................................................................................................... 533
24.4
Flash Memory Control Status Register (FMCS) ............................................................................. 535
24.5
Starting the Flash Memory Automatic Algorithm ............................................................................ 538
24.6
Confirming the Automatic Algorithm Execution State ..................................................................... 539
24.6.1
Data Polling Flag (DQ7) ............................................................................................................ 541
24.6.2
Toggle Bit Flag (DQ6) ................................................................................................................ 542
24.6.3
Timing Limit Exceeded Flag (DQ5) ........................................................................................... 543
24.7
Detailed Explanation of Writing to and Erasing Flash Memory ....................................................... 544
24.7.1
Setting The Read/Reset State ................................................................................................... 545
24.7.2
Writing Data ............................................................................................................................... 546
24.7.3
Erasing All Data (Erasing Chips) ............................................................................................... 548
24.8
Notes on Using 512K-bit Flash Memory ......................................................................................... 550
24.9
Flash Security Feature .................................................................................................................... 551
