FUJITSU F2MCTM-16LX - Manual (Page 256)

240
CHAPTER 14 16-BIT RELOAD TIMER
14.2 Block Diagram of 16-bit Reload Timer
The 16-bit reload timers 2 and 3 composed of the following seven blocks:
• Count clock generator
• Reload controller
• Output controller
• Operation controller
• 16-bit timer register (TMR)
• 16-bit reload register (TMRLR)
• Timer control status register (TMCSR)
■ Block Diagram of 16-bit Reload Timer
Figure 14.2-1 Block Diagram of 16-bit Reload Timer
− − −
CSL1 CSL0 MOD2 MOD1
−
OUTL OUTE RELD INTE UF CNTE TRG MOD0
TMR
TMRLR
TOT EN
TIN
2
3
3
CLK
CLK
Internal data bus
16-bit reload register
Reload signal
16-bit timer register UF
Reload
control
circuit
Valid clock
judgement
circuit
Prescaler
Gate
input
Machine
clock
φ
Wait signal
Input
control
circuit
Clock
selector
Pin
Function selection
External clock
Output control circuit
Output signal
generating
circuit
Pin
Internal
clock
Operating
control circuit
Select
signal
Timer control status register (TMCSR)
Interrupt request
output
Counter clock generating
circuit
Clear