FUJITSU F2MCTM-16LX User Manual

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CHAPTER 8 LOW-POWER CONSUMPTION MODE

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Return by interrupt

When an interrupt request higher than the interrupt level (IL) of 7 is generated from external interrupt in the

stop mode, the stop mode is cancelled. In the stop mode, the main clock oscillation stabilization wait time

or the sub clock oscillation stabilization wait time is generated after the stop mode is cancelled. After the

termination of the main clock oscillation stabilization wait time or subclock oscillation stabilization wait

time, as with normal interrupt processing, the generated interrupt request is identified according to the

settings of the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the

interrupt control register (ICR).

•

When the CPU is not ready to accept any interrupt request, the instruction next to the currently

executing instruction is executed.

•

When the CPU is ready to accept any interrupt request, it immediately branches to the interrupt

processing routine.

Notes:

•

When interrupt processing is executed, the CPU normally executes the instruction following the

instruction in which the stop mode has been specified. The CPU then proceeds to interrupt processing.

When transiting to the PLL stop mode, set the oscillation stabilization wait time selection bits in the

clock selection register (CKSCR: WS1, WS0) to "10

" or "11

•

In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop

mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation

stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are

counted simultaneously according to the value specified in the oscillation stabilization wait time

selection bits in the clock selection register (CKSCR: WS1, WS0). The oscillation stabilization wait

time selection bits in the clock selection register (CKSCR: WS1, WS0) must be selected accordingly to

account for the longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock

oscillation stabilization wait time, however, requires 2

/HCLK or more. Set the oscillation stabilization

wait time selection bits in the clock selection register (CKSCR: WS1, WS0) to "10

" or "11