FUJITSU F2MCTM-16LX - Manual (Page 44)

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CHAPTER 2 CPU
2.1 Outline of the CPU
The F
2
MC-16LX CPU core is a 16-bit CPU designed for applications that require high-
speed real-time processing, such as home-use or vehicle-mounted electronic
appliances. The F
2
MC-16LX instruction set is designed for controller applications, and
is capable of high-speed, highly efficient control processing.
■ Outline of the CPU
In addition to 16-bit data, the F
2
MC-16LX CPU core can process 32-bit data by using an internal 32-bit
accumulator. (32-bit data can be processed with some instructions.) Up to 16M bytes of memory space
(expandable) can be used, which can be accessed by either the linear pointer or bank method. The
instruction system, based on the F
2
MC-8 A-T architecture, has been reinforced by adding instructions
compatible with high-level languages, expanding addressing modes, reinforcing multiplication and division
instructions, and enhancing bit processing. The features of the F
2
MC-16LX CPU are explained below.
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Minimum instruction execution time: 42 ns (at 4-MHz oscillation, 6 times clock multiplication)
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Maximum memory space: 16M bytes, accessed in linear or bank mode
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Instruction set optimized for controller applications
• Rich data types: Bit, byte, word, long word
• Extended addressing modes: 23 types
• High-precision operation (32-bit length) based on 32-bit accumulator
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Powerful interrupt functions
Eight priority levels (programmable)
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CPU-independent automatic transfer
Up to 16 channels of the extended intelligent I/O service
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Instruction set compatible with high-level language (C)/multitasking
System stack pointer/instruction set symmetry/barrel-shift instructions
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Improved execution speed: 4 bytes queue