FUJITSU F2MCTM-16LX - Manual (Page 514)

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CHAPTER 21 CAN CONTROLLER
21.10 Procedure for Reception by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, make the settings
described below.
■ Procedure for Reception by Message Buffer (x)
●
Setting reception interrupt
To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to 1.
To disable reception interrupt, set RIEx to 0.
●
Starting reception
When starting reception after setting, set BVALx of the message buffer valid register (BVALR) to 1 to
make the message buffer (x) valid.
●
Processing for reception completion
If reception is successful after passing to the acceptance filter, the received message is stored in the
message buffer (x) and RCx of the reception complete register (RCR) becomes 1. For data frame reception,
RRTRx of the remote request receiving register (RRTRR) becomes 0. For remote frame reception, RRTRx
becomes 1.
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an interrupt
occurs.
After checking the reception completion (RCx = 1), process the received message.
After completion of processing the received message, check ROVRx of the reception overrun register
(ROVRR).
If ROVRx = 0, the processed received message is valid. Write 0 to RCRx to set it to 0 (the reception
complete interrupt is also canceled) to terminate reception.
If ROVRx = 1, a reception overrun occurred and the next message may have overwritten the processed
message. In this case, received messages should be processed again after setting the ROVRx bit to 0 by
writing 0 to it.
Figure 21.10-1 shows an example of receive interrupt handling.