FUJITSU F2MCTM-16LX - Manual (Page 440)

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CHAPTER 20 LIN-UART
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Transmission operation
If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR) is "1",
transmission data is allowed to be written to the Transmission Data Register (TDR). When data is written,
the TDRE flag goes "0". If the transmission operation is enabled by the TXE-Bit ("1") of the Serial Control
Register (SCR), the data is written next to the transmission shift register and the transmission starts at the
next clock cycle of the serial clock, beginning with the start bit.
If transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag. Note, that the
initial value of the TDRE flag is "1", so that in this case if TIE is set to "1" an interrupt will occur
immediately.
When the data length is set to 7 bits (CL=0), the unused bit of the TDR is always the MSB, independently
from the transfer direction selection in the BDS bit (LSB first or MSB first).
Note:
As the initial value of transmission data empty flag bit (SSR: TDRE) is "1" if the transmission interrupt
is enabled (SSR: TIE=1), the interrupt occurs immediately.
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Reception operation
Reception operation is performed when it is enabled by the Reception Enable (RXE) flag bit of the SCR. If
a start bit is detected, a data frame is received according to the data format specified by the SCR. In case of
errors, the corresponding error flags are set (SSR: PE, ORE, FRE). After the reception of the data frame,
the data is transferred from the reception shift register to the Reception Data Register (RDR) and the
Receive Data Register Full (RDRF) flag bit of the SSR is set to "1". In this case, if the reception interrupt
request is enabled (SSR: RIE=1), the reception interrupt request is occurred. When reading data after
reception of one frame data, check the error flag state and read reception data from the RDR register if the
reception is performed normally. If the reception error occurs, perform error processing. The data then has
to be read by the CPU. By doing so, the RDRF flag of SSR is cleared to "0".
When the data length is set to 7 bits (CL=0), the unused bit of the TDR is always the MSB, independently
from the bit transfer direction selection in the BDS bit (LSB first or MSB first).
Note:
Only when the RDRF flag bit of SSR is set to "1" and no errors have occurred (SSR: PE, ORE, FRE=0)
the Reception Data Register (RDR) contains valid data.
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Used clock
Use the internal clock or external clock. Select the baud rate generator (SMR: EXT = 0 or 1, OTO = 0) for
desired baud rate.