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3 timebase timer mode, Timebase timer mode – FUJITSU F2MCTM-16LX User Manual

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CHAPTER 8 LOW-POWER CONSUMPTION MODE

8.5.3

Timebase Timer Mode

This mode causes all functions, excluding oscillation clock (HCLK), subclock (SCLK),
the timebase timer, the watch timer, and low voltage detection circuit, to stop. In this
mode, only the timebase timer, watch timer, and low voltage detection circuit, operate.

Switching to the Timebase Timer Mode

When 0 is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the

PLL clock mode or main clock mode (CKSCR: SCM = 1), switching to the timebase timer mode occurs.

Data retention function

In the timebase timer mode, the contents of dedicated registers, such as accumulators, and the internal

RAM are retained.

Operation during an interrupt request

Writing 0 in the TMD bit of the low-power consumption mode control register (LPMCR) during an

interrupt request does not trigger a switch to the timebase timer mode.

If the CPU is not ready to accept any interrupt request, the instruction next to currently executing

instruction is executed. If the CPU is ready to accept any interrupt request, an interrupt operation

immediately branches to the interrupt processing routine.

Status of pins

Whether the I/O pins in the timebase timer mode retain the state they had immediately before switching to

the timebase timer mode or go to the high-impedance state can be controlled by the low-power

consumption mode control register (LPMCR: SPL).

Note:

To set the pin that is shared the peripheral function and port to the high impedance in the timebase timer

mode, disable the output of the peripheral function, then set the TMD bit of the low-power consumption

mode control register (LPMCR) to "0".

Return from Timebase Timer Mode

The timebase timer mode is cancelled by a reset factor or when an interrupt is generated.

Return by reset factor

When the timebase timer mode is cancelled by a reset factor, the mode transits to the main clock mode after

the timebase timer mode is cancelled, transiting to the reset sequence.