FUJITSU F2MCTM-16LX - Manual (Page 280)

264
CHAPTER 14 16-BIT RELOAD TIMER
BRA LOOP ;
;---------Interrupt program-----------------------------------
WARI:
CLR I:UF2 ;Interrupt request flag cleared
:
:
Processing by user
:
:
RETI ;Return from interrupt
CODE ENDS
;---------Vector setting----------------------------------------
VECT CSEG ABS=0FFH
ORG 00FFB0H ;Set vector to interrupt #19(13
H
)
DSL WARI
ORG 00FFDCH ;Reset vector set
DSL START
DB 00H ;Set to single-chip mode
VECT ENDS
END START
■ Program Example in Event Counter Mode
●
Processing specification
• An interrupt is generated when rising edges of the pulse input to the external event input pin are counted
10000 times by the 16-bit reload timer 2.
• Operation is performed in the one-shot mode.
• The rising edge is selected for the external trigger input.
• EI
2
OS is not used.
●
Coding example
ICR04 EQU 0000B4H ;Interrupt control register for 16-bit
;reload timer
TMCSR2 EQU 000064H ;Timer control status register
TMR2 EQU 00794CH ;16-bit timer register
TMRLR2 EQU 00794CH ;16-bit reload register
DDR8 EQU 000018H ;Port data register
UF2 EQU TMCSR2:2 ;Interrupt request flag bit
CNTE2 EQU TMCSR2:1 ;Counter operation enable bit
TRG2 EQU TMCSR2:0 ;Software trigger bit
;---------Main program-----------------------------------
CODE CSEG
; : ;Stack pointer (SP), already initialized
;Used at software starting mode(ACS1 :
STS1, 0 = 00
B
)