FUJITSU F2MCTM-16LX - Manual (Page 162)

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CHAPTER 8 LOW-POWER CONSUMPTION MODE
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Operation during an interrupt request
Writing 1 in the SLP bit of the low-power consumption mode control register (LPMCR) during an interrupt
request does not trigger a switch to a sleep mode. If the CPU does not accept the interrupt request, the CPU
executes the next to currently executing instruction. If the CPU accepts the interrupt request, CPU
operation immediately branches to the interrupt processing routine.
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Status of pins
During a sleep mode, all pins retain their previous status.
■ Return from Sleep Mode
The sleep mode is cancelled by a reset factor or when an interrupt is generated.
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Return by reset factor
When the sleep mode is cancelled by a reset factor, the mode transits to the main clock mode after the sleep
mode is cancelled, transiting to the reset sequence.
Note:
• For returning from subsleep mode to main clock mode using the external reset pin (RST pin), input
the Low level for at least oscillator’s oscillation time* + 100 µs + 16 machine cycles (main clock).
*: The oscillation time for the oscillator is the period of time taken until its amplitude reaches 90%.
It takes several to dozens of ms for crystal oscillators, hundreds of µs to several ms for FAR/
ceramic oscillators, and 0 ms for external clocks.
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Return by interrupt
When a higher interrupt request than the interrupt level (IL) of 7 is generated from the resources in the
sleep mode, the sleep mode is cancelled. After the sleep mode is cancelled, as with normal interrupt
processing, the generated interrupt request is identified according to the settings of the I flag in the
condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register
(ICR).
• When the CPU is not ready to accept any interrupt request, the next instruction to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it immediately branches to the interrupt
processing routine.
Figure 8.5-1 shows the release of a sleep mode when an interrupt occurs.