FUJITSU F2MCTM-16LX - Manual (Page 276)

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CHAPTER 14 16-BIT RELOAD TIMER
■ Operation as 16-bit Timer Register Underflows
When the value of the 16-bit timer register (TMR) is decremented from "0000
H
" to "FFFF
H
" during the
TMR count operation, an underflow occurs.
• When an underflow occurs, the underflow generating flag bit in the timer control status register
(TMCSR:UF) is set to 1.
• When the underflow interrupt enable bit in the timer control status register (TMCSR:INTE) is set to 1,
an underflow interrupt is generated.
• The reload operation when an underflow occurs is set by the reload select bit in the timer control status
register (TMCSR:RELD).
[One-shot mode (TMCSR: RELD=0)]
When an underflow occurs, the TMR count operation is stopped, entering the start trigger input wait state.
When the next start trigger is inputted, the TMR count operation is restarted.
In the one-shot mode, a rectangular wave is outputted from the TOT pin during the TMR count operation.
The pin output level select bit in the timer control status register (TMCSR:OUTL) can be set to select the
level (High or Low) of the rectangular wave.
[Reload mode (TMCSR: RELD=1)]
When an underflow occurs, the value set in the TMRLR is reloaded to the TMR, continuing the TMR count
operation.
In the reload mode, a toggle wave inverting the output level of the TOT pin is outputted each time an
underflow occurs during the TMR count operation. The pin output level select bit in the timer control status
register (TMCSR:OUTL) can be set to select the level (High or Low) of the toggle wave when the 16-bit
reload timer is started.