FUJITSU F2MCTM-16LX - Manual (Page 526)

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CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
Table 22.3-1 Functions of Address Detection Control Register (PACSR0)
Bit Name Function
bit7,
bit6
Reserved: reserved bits Always set to 0.
bit5 AD2E:
Address match detec-
tion enable bit 2 The address match detection operation with the detect address setting register 2
(PADR2) is enabled or disabled.
When set to 0: Disables the address match detection operation.
When set to 1: Enables the address match detection operation.
•
When the value of detect address setting registers 2 (PADR2) matches with
the value of address latch at enabling the address match detection operation
(AD2E = 1), the INT9 instruction is immediately executed.
bit4 Reserved: reserved bit Always set to 0.
bit3 AD1E:
Address match
detection enable bit 1 The address match detection operation with the detect address setting register 1
(PADR1) is enabled or disabled.
When set to 0: Disables the address match detection operation.
When set to 1: Enables the address match detection operation.
•
When the value of detect address setting registers 1 (PADR1) matches with
the value of address latch at enabling the address match detection operation
(AD1E = 1), the INT9 instruction is immediately executed.
bit2 Reserved: reserved bit Always set to 0.
bit1 AD0E:
Address match
detection enable bit 0 The address match detection operation with the detect address setting register 0
(PADR0) is enabled or disabled.
When set to 0: Disables the address match detection operation.
When set to 1: Enables the address match detection operation.
•
When the value of detect address setting registers 0 (PADR0) matches with
the value of address latch at enabling the address match detection operation
(AD0E = 1), the INT9 instruction is immediately executed.
bit0 Reserved: reserved bit Always set to 0.