FUJITSU F2MCTM-16LX - Manual (Page 151)

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CHAPTER 8 LOW-POWER CONSUMPTION MODE
■ Clock Mode
●
PLL clock mode
In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and
peripheral functions.
●
Main clock mode
In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate
the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive.
●
Sub-clock mode
In this mode, the sub-clock (SCLK) is used to operate the CPU and peripheral functions. The sub-clock can
select a clock frequency divided by 2 or 4 of clock from external sub-clock pin or internal CR oscillation
clock.
In the sub-clock mode, the main clock and PLL multiplier circuit are inactive.
The subclock oscillation stabilization wait time of 2
14
/SCLK (Approx. 2 s @32.768 kHz oscillation clock
frequency, 1/4 division) takes place when power-on and reactivation from stop mode. If a transition from
main clock mode to subclock mode is performed during this oscillation stabilization wait time, actual
transition may be delayed.
Reference:
For the clock mode, see "5.5 Clock Mode".
■ CPU Intermittent Operating Mode
In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral
functions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to
the CPU while it is accessing a register, internal memory, peripheral function, or external unit.
■ Standby Mode
In this mode, the standby control circuit stops supplying the clock to the CPU or peripheral functions or
stops the oscillation clock itself (HCLK), thereby reducing power consumption.
●
Sleep mode
The sleep mode stops the operation clock to the CPU during operation in each clock mode. The CPU stops,
and the peripheral function operates the clock before the transition to the sleep mode. The sleep mode is
divided into the main sleep mode, PLL sleep mode before the transition to sleep mode.
●
Watch mode
The watch mode operates the sub-clock (SCLK), watch timer, and low voltage detection circuit only. The
main clock and PLL clock stop. All peripheral functions other than the watch timer and low voltage
detection circuit stop.