FUJITSU F2MCTM-16LX - Manual (Page 516)

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CHAPTER 21 CAN CONTROLLER
21.11 Setting Configuration of Multi-level Message Buffer
If the receptions are performed frequently, or if several different ID’s of messages are
received, in other words, if there is insufficient time for handling messages, more than 1
message buffer can be combined into a multi-level message buffer to provide allowance
for processing time of the received message by CPU.
■ Setting Configuration of Multi-level Message Buffer
To provide a multi-level message buffer, the same acceptance filter must be set in the combined message
buffers.
If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare ((AMSx.1, AMSx.0)
= (0, 0)), multi-level message configuration of message buffers is not allowed. This is because All Bits
Compare causes received messages to be stored irrespective of the value of the RCx bit of the receive
completion register (RCR), so received messages are always stored in lower-numbered (higher-priority)
message buffers even if All Bits Compare and identical acceptance code (ID register (IDRx)) are specified
for more than 1 message buffer. Therefore, All Bits Compare and identical acceptance code should not be
specified for more than 1 message buffer.
Figure 21.11-1 shows operational examples of multi-level message buffers.