FUJITSU F2MCTM-16LX - Manual (Page 106)

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CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE
4.6 Program Example of Delayed Interrupt Generation Module
This section gives a program example of the delayed interrupt generation module.
■ Program Example of Delayed Interrupt Generation Module
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Processing specification
The main program writes "1" to the R0 bit in the delayed interrupt request generate/cancel register (DIRR)
to generate a delayed interrupt request and performs task switching.
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Coding example
ICR15 EQU 0000BFH ;Interrupt control register
DIRR EQU 00009FH ;Delayed interrupt factor generate/
cancel register
DIRR_R0 EQU DIRR:0 ;Delay interrupt request generating bit
;---------Main program------------------------------------
CODE CSEG
START: ;Stack pointer (SP),already initialized
AND CCR,#0BFH ;Interrupt disabled
MOV I:ICR15,#00H ;Interrupt level 0 (strong)
MOV ILM,#07H ;Setting ILM in PS to level 7
OR CCR,#40H ;Interrupt enabled
SETB I:DIRR_R0 ;Delay interrupt request generating
LOOP MOV A,#00H ;No limit loop
MOV A,#01H
BRA LOOP
;---------Interrupt program--------------------------------------
WARI:
CLRB I:DIRR_R0 ;Clear interrupt request flag
:
; User processing
; :
RETI ;Recovery from interrput
CODE ENDS
;---------Vector setting-----------------------------------------
VECT CSEG ABS=0FFH
ORG 0FF54H ;Setting vector to interrupt #42 (2AH)
DSL WARI
ORG 0FFDCH ;Reset vector setting
DSL START
DB 00H ;Setting to single-chip mode
VECT ENDS
END START