FUJITSU F2MCTM-16LX - Manual (Page 199)

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CHAPTER 11 TIMEBASE TIMER
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Timebase timer counter
The timebase timer counter is an 18-bit up counter that uses a clock with a half frequency of the oscillation
clock (HCLK) as a count clock.
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Counter clear circuit
The counter clear circuit clears the value of the timebase timer counter by the following factors:
• Timebase timer counter clear bit in the timebase timer control register (TBTC: TBR=0)
• Power-on reset
• Transition to main stop mode or PLL stop mode (CKSCR:SCS=1, LPMCR: STP=1)
• Switching the clock mode (from main clock mode to PLL clock mode, from subclock mode to PLL
clock mode, or from subclock mode to main clock mode)
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Interval timer selector
The interval timer selector selects the output of the timebase timer counter from four types.
When incrementing causes the selected interval time bit to overflow (carrying), an interrupt request is
generated.
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Timebase timer control register (TBTC)
The timebase timer control register (TBTC) selects the interval time, clears the timebase timer counter,
enables or disables interrupts, and checks and clears the state of an interrupt request.