FUJITSU F2MCTM-16LX - Manual (Page 164)

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CHAPTER 8 LOW-POWER CONSUMPTION MODE
8.5.2 Watch Mode
This mode causes all functions, excluding the subclock (SCLK), watch timer, and low
voltage detection circuit, to stop. Main clock and PLL clock stop.
■ Switching to the Watch Mode
When 0 is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the
subclock run mode, switching to the watch mode occurs.
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Data retention function
In the watch mode, the contents of the dedicated registers, such as accumulators, and the internal RAM are
retained.
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Operation during an interrupt request
Writing 1 in the TMD bit of the low-power consumption mode control register (LPMCR) during an
interrupt request does not trigger a switch to the watch mode.
If the CPU is not ready to accept any interrupt request, the instruction next to currently executing
instruction is executed. If the CPU is ready to accept any interrupt request, an interrupt operation
immediately branches to the interrupt processing routine.
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Status of pins
Whether the I/O pins in the watch mode retain the state they had immediately before switching to the watch
mode or go to the high-impedance state can be controlled by the SPL bit of the low-power consumption
mode control register (LPMCR).
Note:
To set the pin that is shared the peripheral function and port to the high impedance in the watch mode,
disable the output of peripheral function, then set the TMD bit of the low-power consumption mode
control register (LPMCR) to "0".
■ Return from Watch Mode
The watch mode is cancelled by a reset factor or when an interrupt is generated.
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Return by reset factor
When the watch mode is cancelled by a reset factor, the mode transits to the main clock mode after the
watch mode is cancelled, transiting to the reset sequence.
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Return by interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from the watch
timer and external interrupt in the watch mode, the watch mode is cancelled. After the watch
mode is cancelled, as with normal interrupt processing, the generated interrupt request is