FUJITSU F2MCTM-16LX - Manual (Page 92)

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CHAPTER 3 INTERRUPTS
3.7.1 Extended Intelligent I/O Service Descriptor (ISD)
The extended intelligent I/O service descriptor exists between 000100
H
and 00017F
H
in
internal RAM and consists of the following items:
• Data transfer control data
• Status data
• Buffer address pointer
■ Extended Intelligent I/O Service Descriptor (ISD)
Figure 3.7-2 shows the configuration of the extended intelligent I/O service descriptor.
Figure 3.7-2 Extended Intelligent I/O Service Descriptor Configuration
■ Data Counter (DCT)
This is a 16-bit register that works as a counter corresponding to the number of data items transferred. This
counter is decremented by one before data transfer. EI
2
OS is terminated when this counter reaches 0.
Figure 3.7-3 is a diagram of the data counter configuration.
Figure 3.7-3 Data Counter Configuration
High-order 8 bits of data counter (DCTH)
Low-order 8 bits of data counter (DCTL)
High-order 8 bits of I/O address pointer (IOAH)
Low-order 8 bits of I/O address pointer (IOAL)
EI 2 OS status (ISCS)
High-order 8 bits of buffer address pointer (BAPH)
Midium-order 8 bits of buffer address pointer (BAPM)
Low-order 8 bits of buffer address pointer(BAPL)
H
L
ISD start address
000100
H
ICS
B15 B08 B07 B04 B10
DCT
(Undefined
when reset) B14 B13 B12 B11 B09 B00 B01 B02 B03 B05 B06
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15