FUJITSU F2MCTM-16LX - Manual (Page 674)

658
INDEX
LIN-master-slave Communication
LIN-master-slave Communication Function ........ 438
LIN-UART
Block Diagram of LIN-UART ........................... 387
Block Diagram of LIN-UART Pins .................... 391
LIN-UART as LIN Master Device ..................... 439
LIN-UART Baud Rate Selection ........................ 413
LIN-UART Direct Pin Access ........................... 432
LIN-UART Functions ....................................... 382
LIN-UART Interrupts ....................................... 406
LIN-UART Interrupts and EI
2
OS ....................... 408
LIN-UART Pins ............................................... 391
LIN-UART Registers ........................................ 392
Notes on Using LIN-UART ............................... 441
Operation of LIN-UART ................................... 420
LIN-UART Serial Mode Register
LIN-UART Serial Mode Register (SMR) ........... 395
Low Voltage
Block Diagram of Low Voltage/CPU Operating
Detection Reset Circuit ........................ 374
Operating of Low Voltage/CPU Operating Detection
Reset Circuit ....................................... 378
Sample Program for Low Voltage/CPU Operating
Detection Reset Circuit ........................ 380
Low Voltage Detection
Status of Reset Cause Bit and Low Voltage Detection
Bit ..................................................... 130
Low Voltage Detection Reset Circuit
Low Voltage Detection Reset Circuit ................. 372
Notes on Using Low Voltage Detection Reset Circuit
.......................................................... 379
Low Voltage/CPU Operating Detection Reset Control
Register
Low Voltage/CPU Operating Detection Reset
Control Register (LVRC) ..................... 376
Low-Power Consumption
Block Diagram of the Low-Power Consumption
Control Circuit .................................... 137
Low-Power Consumption Mode Control Register
Low-Power Consumption Mode Control Register
(LPMCR) ........................................... 139
Notes on Accessing the Low-Power Consumption
Mode Control Register (LPMCR) to
Enter the Standby Mode
....................... 158
LPMCR
Low-Power Consumption Mode Control Register
(LPMCR) ........................................... 139
Notes on Accessing the Low-Power Consumption
Mode Control Register (LPMCR) to
Enter the Standby Mode ....................... 158
LVRC
Low Voltage/CPU Operating Detection Reset Control
Register (LVRC) ................................. 376
M
Machine Clock
Machine Clock ................................................ 104
Mask ROM
Block Diagram of Flash/Mask ROM Version ....... 11
Master-slave Communication
Master-slave Communication Function .............. 435
MB90360 Series
Features of MB90360 Series ................................. 2
MB90F362
Basic Configuration of Serial Programming
Connection with MB90F362/T(S),
MB90F367/T(S)
................................. 554
MB90F367
Basic Configuration of Serial Programming
Connection with MB90F362/T(S),
MB90F367/T(S)
................................. 554
MB90V340
CAN Direct Mode Register (CDMR)
(Only MB90V340) .............................. 502
MD
Continuous Conversion Mode
(ADCS:MD1,MD0= "10
B
" ) ................ 359
Pause-conversion Mode
(ADCS:MD1,MD0= "11
B
" ) .................. 359
Single-shot Conversion Mode
(ADCS:MD1,MD0= "00
B
" or "01
B
" )
................................................................ 359
Memory Access Modes
Outline of Memory Access Modes ..................... 162
Memory Map
E
2
PROM Memory Map .................................... 518
Memory Map ..................................................... 32
System Configuration and E
2
PROM Memory Map
......................................................... 517
Memory Space
Memory Space in Each Bus Mode ..................... 165
Multi-byte Data Allocation in Memory Space ....... 36
Outline of CPU Memory Space ........................... 29
Message Buffer
Caution for Disabling Message Buffers by BVAL Bits
......................................................... 503
List of Message Buffer (data register) ................ 451
List of Message Buffers (DLC registers and Data
registers) ............................................ 450
List of Message Buffers (ID registers) ................ 448
Message Buffers ...................................... 452, 481
Procedure for Reception by Message Buffer (x)
......................................................... 498
Procedure for Transmission by Message Buffer (x)
......................................................... 496
Setting Configuration of Multi-level Message Buffer
......................................................... 500