FUJITSU F2MCTM-16LX - Manual (Page 200)

184
CHAPTER 11 TIMEBASE TIMER
11.3 Configuration of Timebase Timer
This section explains the registers and interrupt factors of the timebase timer.
■ List of Registers and Reset Values of Timebase Timer
Figure 11.3-1 List of Registers and Reset Values of Timebase Timer
■ Generation of Interrupt Request from Timebase Timer
When the selected interval timer counter bit reaches the interval time, the overflow interrupt request flag bit
in the timebase timer control register (TBTC: TBOF) is set to "1". If the overflow interrupt request flag bit
is set (TBTC: TBOF = 1) when the interrupt is enabled (TBTC: TBIE = 1), the timebase timer generates an
interrupt request.
0 0 0 1 1 0
15 14 bit 13 12 11 10 9 8
Timebase timer control register
(TBTC)
: Undefined