FUJITSU F2MCTM-16LX - Manual (Page 111)

95
CHAPTER 5 CLOCKS
5.2 Block Diagram of the Clock Generation Block
The clock generation block consists of five blocks:
• System clock generation circuit/sub-clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• PLL/sub-clock control register (PSCCR)
• Oscillation stabilization wait interval selector
■ Block Diagram of the Clock Generation Block
Figure 5.2-1 shows a block diagram of the clock generation block. The figure also includes the standby
control circuit and timebase timer circuit.
Figure 5.2-1 Block Diagram of the Clock Generation Block
PLL multiplier
circuit
CPU clock
Control circuit
Peripheral Clock
Control circuit
Reset (Clear)
Interrupt (Clear)
CPU operating clock
Peripheral function
operating clock
Standby
Control circuit
Timebase timer
Clock timer
To watchdog timer
oscillation clock
oscillation circuit
Subclock oscillation circuit
Subclock
(SCLK)
Clock
generator
Operation clock
selector
Machine
Clock
Oscillation
stabilization
wait time selector
oscillation
clock (HCLK)
X0
2
X1
Clock selection register (CKSCR)
Low-Power consumption Mode Control Register(LPMCR)
Time, sleep, stop sign
Time, stop sign
Select the intermitted cycle
Internal reset
generator
Terminal high
impedance
Control circuit
Internal reset
Pin High-z control
Pin RST
Pin
Pin
STP RST SLP CG1 CG0
Reserved
SPL TMD
SCM WS0 MCM MCS CS1 CS0 WS1 SCS
2
2
Main clock oscillation stabilization wait clear
Subclock oscillation stabilization wait clear
X0A
X1A
Pin
Pin
Main
clock
PLL/Subclock
Control register
(PSCCR):bit8
CS2
PLL/Subclock
control register
(PSCCR):bit10
SCDS
8-
divided
1024
-divided
2-
divided
2-
divided
2-
divided
2-
divided
2-
divided
2-
divided
2-
divided
4-
divided
4-
divided
512-
divided
2-
divided
4-divided/
2-divided
CPU intermittent
operation cycle
selector
Clock
selector
Clock
selector
Internal CR oscillation clock
Clock supervisor function