FUJITSU F2MCTM-16LX - Manual (Page 669)

653
INDEX
Clock Supervisor Control Register
Clock Supervisor Control Register (CSVCR) ...... 113
Clock Supply
Cycle of Clock Supply ...................................... 269
Clocks
Clocks ............................................................... 92
CMR
Common Register Bank Prefix (CMR) ................. 49
Command Sequence
Chip Erase/sector Erase Command Sequence ...... 639
Command Sequence Table ................................ 538
Common Register Bank Prefix
Common Register Bank Prefix (CMR) ................. 49
Communication
Bidirectional Communication Function .............. 433
LIN-master-slave Communication Function ....... 438
Master-slave Communication Function .............. 435
Comparing Time
Setting of Comparing Time (CT2 to CT0 bits)
.......................................................... 355
Condition Code Register
Condition Code Register (CCR) .......................... 42
Configuration of the Clock Selection Register
Configuration of the Clock Selection Register
(CKSCR) ............................................. 98
Configuration of the PLL/Subclock Control Register
Configuration of the PLL/Subclock Control Register
(PSCCR) ............................................ 101
Continuous Conversion Mode
Continuous Conversion Mode
(ADCS: MD1,MD0= "10
B
") ................ 359
Operation of Continuous Conversion Mode ........ 363
Setting of Continuous Conversion Mode ............ 362
Control Status Register
Control Status Register (CSR) (Lower) .............. 453
Control Status Register (CSR) (upper) ............... 453
Control Status Register (CSR-lower) ................. 454
Conversion
Conversion Using EI
2
OS .................................. 366
Conversion Mode
Continuous Conversion Mode
(ADCS:MD1,MD0= "10
B
") ................. 359
Conversion Modes of 8-/10-bit A/D Converter
.......................................................... 340
Operation of Continuous Conversion Mode ........ 363
Operation of Pause-conversion Mode ................. 365
Operation of Single-shot Conversion Mode ........ 361
Pause-conversion Mode (ADCS:MD1,MD0= "11
B
")
.......................................................... 359
Setting of Continuous Conversion Mode ............ 362
Setting of Pause-conversion Mode ..................... 364
Setting of Single-shot Conversion Mode ............ 360
Single-shot Conversion Mode
(ADCS:MD1,MD0= "00
B
" or "01
B
")
..........................................................359
Counting Example
Counting Example ............................................417
CPU
Outline of CPU Memory Space ............................29
Outline of the CPU .............................................28
CPU Intermittent Operating Mode
CPU Intermittent Operating Mode ......................135
CPU Intermittent Operation Mode
CPU Intermittent Operation Mode ......................142
CPU Operating Detection Reset Circuit
Block Diagram of Low Voltage/CPU Operating
Detection Reset Circuit ........................374
CPU Operating Detection Reset Circuit ..............373
Notes on Using CPU Operating Detection Reset
Circuit ................................................379
Operating of CPU Operating Detection Reset Circuit
..........................................................378
Operating of Low Voltage/CPU Operating Detection
Reset Circuit .......................................378
Sample Program for Low Voltage/CPU Operating
Detection Reset Circuit ........................380
CPU Operating Modes
CPU Operating Modes and Current Consumption
..........................................................134
CR Oscillation Circuit
Prohibition Setting of CR Oscillation Circuit and
Clock Supervisor .................................115
Reoperating Setting of CR Oscillation Circuit and
Clock Supervisor .................................115
CSR
Control Status Register (CSR) (Lower) ...............453
Control Status Register (CSR) (upper) ................453
Control Status Register (CSR-lower) ..................454
CSVCR
Clock Supervisor Control Register (CSVCR) ......113
CT
Setting of Comparing Time (CT2 to CT0 bits) .....355
Current Consumption
CPU Operating Modes and Current Consumption
..........................................................134
Cycle Count
Execution Cycle Count ......................................593
D
Data Counter
Data Counter (DCT) ...........................................76
Data Frame
Processing for Reception of Data Frame and Remote
frame ..................................................491
Data Polling
Data Polling .....................................................640