FUJITSU F2MCTM-16LX - Manual (Page 403)

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CHAPTER 20 LIN-UART
■ Block Diagram of LIN-UART
Figure 20.2-1 Block Diagram of LIN-UART
RDRn TDRn
PEN
P
SBL
CL
A/D
CRE
RXE
TXE
MD1
MD0
OTO
EXT
REST
USCKE
USOE
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
LBIE
LBD
SOPE
SIOP
CCO
SCES
LBIE
LBD
RBI
RIE
TIE
IRQ
IRQ
LBD
SINn
PE ORE FRE
CLK
SINn
SOTn
MS
SSM
SCDE
TDRE
RDRF
RBI
TBI
UPCL
OTO,
EXT,
REST
PE
ORE
FRE
TBI
RBI TBI
SINn
SCKn
SOTn
SSRn
register SMRn
register SCRn
register ESCRn
register ECCRn
LBR
LBR
LBL1
LBL0
LBL1
LBL0
Internal data bus
Reload
counter
Restart reception
reload counter
Over-
sampling
unit
Pin
Pin
Transmission clock
Reception clock
Reception
control circuit
Start bit
detection
circuit
Received bit
counter
Received
parity counter
Transmission
start circuit
Transmission
bit counter
Transmission
parity counter
Transmission
control circuit
Interrupt
generation
circuit
Reception
Transmission
Pin
Internal signal
to capture LIN break/
SynchField
detection
circuit
To EI 2 OS
Error
detection
Reception
shift register
Transmission
shift register
Transmission
start
LIN break
generation
circuit
Bus idle
detection
circuit
n = 0, 1