FUJITSU F2MCTM-16LX - Manual (Page 321)

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CHAPTER 16 8-/16-BIT PPG TIMER
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Operation in 16-bit PPG output operation mode
• When either PPGn pin output or PPGm pin output is enabled (PPGCn:PEC=1, PPGCm: PED=1), the
same pulse wave is outputted from both the PPGn and PPGm pins.
• When the reload value is set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) to enable
operation of the PPG timer (PPGCn:PENC=1 and PPGCm: PEND=1), the PPG down counters start
counting as 16-bit down counters (PCNTn + PCNTm).
• To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both
channels (PPGCn: PENC=0 and PPGCm: PEND=0). The count operation of the PPG down counters is
stopped and the output of the PPG output pin is held at a Low level.
• If the PPGm down counter underflows, the reload values set in the PPGn and PPGm reload registers
(PRLLn/PRLHn, PRLLm/PRLHm) are reloaded simultaneously to the PPG down counters (PCNTn +
PCNTm).
• When an underflow occurs, the underflow generation flag bits in both channels are set simultaneously
(PPGCn:PUFC=1, PPGCm:PUFD=1). If an interrupt request is enabled at either channel (PPGCn:
PIEC=1, PPGCm: PIED=1), an interrupt request is generated.
Notes:
• In the 16-bit PPG output operation mode, the underflow generation flag bits in the two channels are set
simultaneously when an underflow occurs (PPGCn: PUFC=1 and PPGCm: PUFD=1). To prevent
duplication of interrupt requests, disable either of the underflow interrupt enable bits in the two channels
(PPGCn:PIEC=0, PPGCm:PIED=1 or PPGCn:PIEC=1, PPGCm:PIED=0).
• If the underflow generation flag bits in the two channels are set (PPGCn: PUFC=0 and PPGCm:
PUFD=0), clear the two channels at the same time.
Note: n = C, E
m = n+1