FUJITSU F2MCTM-16LX - Manual (Page 677)

661
INDEX
PSCCR
Configuration of the PLL/Subclock Control Register
(PSCCR) ............................................ 101
PUCR
Block Diagram of Pull-up Control Register (PUCR)
.......................................................... 174
Pull-up Control Register (PUCR) ...................... 174
Pull-up Control Register
Block Diagram of Pull-up Control Register (PUCR)
.......................................................... 174
Pull-up Control Register (PUCR) ...................... 174
R
RAM
RAM area ......................................................... 30
RDR
Reception Data Register (RDR) ......................... 399
Read
Setting the Flash Memory to the Read/reset State
.......................................................... 545
Read Access
Data Read by Read Access ................................ 636
Receive Overrun
Receive Overrun .............................................. 491
Received Message
Storing Received Message ................................ 490
Reception
Completing Reception ...................................... 492
Procedure for Reception by Message Buffer (x)
.......................................................... 498
Processing for Reception of Data Frame and Remote
Frame ................................................ 491
Reception Flowchart of the CAN Controller ....... 493
Reception Data Register
Reception Data Register (RDR) ......................... 399
Reception Interrupt
Reception Interrupt Generation and Flag Set Timing
.......................................................... 409
Register Bank
Register Bank .................................................... 46
Register Bank Pointer
Register Bank Pointer (RP) ................................. 43
Reload Counter
Function of Reload Counter .............................. 418
Reload Timer
16-bit Reload Timer Registers and Reset Value
.......................................................... 243
Block Diagram of 16-bit Reload Timer .............. 240
Correspondence between 16-bit Reload Timer
Interrupt and EI
2
OS ............................. 251
EI
2
OS Function of 16-bit Reload Timer ............. 251
Generation of Interrupt Request from 16-bit
Reload Timer ...................................... 244
Interrupts of 16-bit Reload Timer ...................... 251
Operation Modes of 16-bit Reload Timer ............238
Pins of 16-bit Reload Timer ...............................242
Precautions when Using 16-bit Reload Timer
..........................................................262
Setting of 16-bit Reload Timer ...........................252
Remote Frame
Processing for Reception of Data Frame
and Remote Frame ...............................491
Reset
16-bit Reload Timer Registers and Reset Value
..........................................................243
Block Diagrams of the External Reset Pin ...........125
Causes of a Reset ..............................................120
Clock Selection Register and List of Reset Value
............................................................97
List of Registers and Reset Values .......................86
List of Registers and Reset Values in DTP/
External Interrupt .................................318
List of Registers and Reset Values of 8-/10-bit
A/D Converter .....................................345
List of Registers and Reset Values of 8-/16-bit
PPG Timer ..........................................291
List of Registers and Reset Values of Address
Match Detection Function ....................508
List of Registers and Reset Values of ROM
Mirroring Function Select Module .........527
List of Registers and Reset Values of Timebase Timer
..........................................................184
List of Registers and Reset Values of Watch Timer
..........................................................272
List of Registers and Reset Values of Watchdog Timer
..........................................................201
Oscillation Stabilization Wait and Reset State .....124
Overview of Reset Operation .............................126
Reset Check By Clock Supervisor ......................117
Status of Pins during a Reset ..............................132
Reset Cause
Reset Cause Bits ...............................................128
Reset Cause
Notes about Reset Cause Bits .............................131
Reset Causes and Oscillation Stabilization Wait Times
..........................................................123
Status of Reset Cause Bit and Low Voltage Detection
Bit ......................................................130
Reset State
Setting the Flash Memory to the Read/reset State
..........................................................545
ROM Mirroring
Access to FF Bank by ROM Mirroring Function
..........................................................526
Block Diagram of ROM Mirroring Function Select
Module ...............................................526
ROM Mirroring Function Select Module
Block Diagram of ROM Mirroring Function Select
Module ...............................................526