FUJITSU F2MCTM-16LX - Manual (Page 313)

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CHAPTER 16 8-/16-BIT PPG TIMER
Table 16.3-4 Functions of PPGC/D Count Clock Select Register (PPGCD)
Bit Name Function
bit7
to
bit5
PCS2 to PCS0:
PPGD count clock select bits These bits set the count clock of the 8-/16-bit PPG timer D.
• The count clock can be selected from five frequency-divided clocks of
the machine clock and the frequency-divided clocks of the timebase
timer.
• The settings of the PPGD count clock select bits (PCS2 to PCS0) are
enabled only in the 8-bit PPG output 2-channel independent mode
(PPGCD: MD1, MD0="00
B
").
bit4
to
bit2
PCM2 to PCM0:
PPGC count clock select bits These bits set the count clock of the 8-/16-bit PPG timer C.
• The count clock can be selected from five frequency-divided clocks of
the machine clock and the frequency-divided clocks of the timebase
timer.
bit1 Undefined bit Read: The value is undefined.
Write: No effect
bit0 REV:
PPG output pin select bit This bit switches the output pin in the 8-/16-bit PPG timer C and D.
When set to "0": Output from the standard output pin.
PPGC
→
PPGC output pin
PPGD
→
PPGD output pin
When set to "1": Switch the output pin.
PPGC → PPGD output pin
PPGD
→
PPGC output pin