FUJITSU F2MCTM-16LX - Manual (Page 346)

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CHAPTER 17 DTP/EXTERNAL INTERRUPTS
Figure 17.4-2 Operation of DTP/External Interrupt
ICR:ISE
0
1
ELVR1
EIRR1
ENIR1
ICR YY
ICR XX
CMP
IL
ILM
CMP
CPU
Recovery from
EI
2 OS processing
(DTP processing)
EI 2 OS starting
=0
0
Interrupt processing
Reset or stop
Recovery from DTP processing
Memory
Peripheral data
transfer
Renewal of descriptor
Descriptor data
counter
Recovery from external interrupt
DTP/external interrupt
request generating
Interrupt controller
reception judge
CPU interrupt
reception judge
Interrupt processing
microprogram starting
External interrupt starting
Processing and interrupt
flag clear
DTP/external interrupt circuit
Factor
Other
request Interrupt controller
Interrupt
processing