FUJITSU F2MCTM-16LX - Manual (Page 527)

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CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
■ Address Detection Control Register 1 (PACSR1)
Figure 22.3-3 Address Detection Control Register 1 (PACSR1)
12 13 11 10 9 8 15 14
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 3 B H
0 0 0 0 0 0 0 0 B
AD3E AD4E AD5E
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
Address Reset value
bit 8
Reserved Reserved bit
0 Always set to "0".
bit 9
AD3E Address match detection enable bit 3
0 Disables address match detection in PADR3.
1 Enables address match detection in PADR3.
R/W Read/Write
: Reset value
bit 10
Reserved Reserved bit
0 Always set to "0".
bit 11
AD4E Address match detection enable bit 4
0 Disables address match detection in PADR4.
1 Enables address match detection in PADR4.
bit 12
Reserved Reserved bit
0 Always set to "0".
bit 13
AD5E Address match detection enable bit 5
0 Disables address match detection in PADR5.
1 Enables address match detection in PADR5.
bit 14
Reserved Reserved bit
0 Always set to "0".
bit 15
Reserved Reserved bit
0 Always set to "0".