FUJITSU F2MCTM-16LX - Manual (Page 133)

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CHAPTER 6 CLOCK SUPERVISOR
■ Reset Check By Clock Supervisor
To check whether reset was executed by the clock supervisor, the WDTC register is read with software and
the reset factor is checked. When ERSR (bit4 of WDTC) is set, the factor is a reset from an external
terminal or a reset by the clock supervisor (include low voltage detection/CPU operating detection reset in
"T" suffix products). If both SM and MM bits (bit5 and bit6 of CSVCR) are 0, the reset factor is an external
reset (include low voltage detection/CPU operating detection reset in "T" suffix products). If SM is 1, the
reset factor is a sub-clock lost. If MM is 1, the reset factor is a main-clock lost.