FUJITSU F2MCTM-16LX - Manual (Page 528)

512
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
Table 22.3-2 Functions of Address Detection Control Register (PACSR1)
Bit Name Function
bit15,
bit14
Reserved: reserved bit Always set to 0.
bit13 AD5E:
Address match detec-
tion enable bit 5 The address match detection operation with the detect address setting register 5
(PADR5) is enabled or disabled.
When set to 0: Disables the address match detection operation.
When set to 1: Enables the address match detection operation.
•
When the value of detect address setting registers 5 (PADR5) matches with
the value of address latch at enabling the address match detection operation
(AD5E = 1), the INT9 instruction is immediately executed.
bit12 Reserved: reserved bit Always set to 0.
bit11 AD4E:
Address match
detection enable bit 4 The address match detection operation with the detect address setting register 4
(PADR4) is enabled or disabled.
When set to 0: Disables the address match detection operation.
When set to 1: Enables the address match detection operation.
•
When the value of detect address setting registers 4 (PADR4) matches with
the value of address latch at enabling the address match detection operation
(AD4E = 1), the INT9 instruction is immediately executed.
bit10 Reserved: reserved bit Always set to 0.
bit9 AD3E:
Address match
detection enable bit 3 The address match detection operation with the detect address setting register 3
(PADR3) is enabled or disabled.
When set to 0: Disables the address match detection operation.
When set to 1: Enables the address match detection operation.
•
When the value of detect address setting registers 3 (PADR3) matches with
the value of address latch at enabling the address match detection operation
(AD3E = 1), the INT9 instruction is immediately executed.
bit8 Reserved: reserved bit Always set to 0.