FUJITSU F2MCTM-16LX - Manual (Page 126)

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CHAPTER 6 CLOCK SUPERVISOR
6.1 Overview of Clock Supervisor
The clock supervisor checks the oscillation of the main clock or a sub-clock (without
"S" suffix product). When the main clock or a sub-clock stops due to some breakdowns,
the control circuit of the clock supervisor switches the clock source to built-in CR
oscillation clock, sets the detection flag, and generates reset.
■ Overview of Clock Supervisor
The clock supervisor checks the oscillation of the main clock or the sub-clock. If the using (main or sub)
clock stops during the fixed time (20
µs to 80 µs: When the main clock is used, 160 µs to 640 µs: When the
sub clock is used), the corresponding clock stop detection flag is set and reset is generated after switching
the stopped clock to the CR oscillation clock.
The reset factor can be checked by the reset factor bit of watchdog timer control register (WDTC).
Supervising a main and a sub-clock can be set to the disable (watching prohibition) respectively
independently.
When a sub-clock stops while the device is operating in the main clock mode, internal reset is not generated
at once. When changing to the sub-clock mode, internal reset is generated. It is also possible to control the
internal reset generation by the setting in this case.
When the device changes to the stop mode, the main-/sub-clock supervisor is automatically disabled
(watching prohibition). Either of main or sub clock supervisor that is the condition that was enable before
the stop mode changed automatically returns from disabled to enabled when returning from the stop mode.
Built-in CR oscillation clock can be used as a sub-clock of the device if the product is the external single-
clock product (with "S" suffix product).
Note:
At power-on, the clock supervisor starts monitoring immediately after a lapse of the oscillation stability
waiting time for the main clock.