Delta DVP-ES2 - Manual (Page 406)

D V P - E S 2 / E X 2 / S S 2 / S A2 / S X 2 / S E O p e r a t i o n M a n u a l - P r o g r a m m i n g
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API Mnemonic Operands Function
107 LRC P LRC checksum
Controllers
ES2/EX2 SS2 SA2
SE
SX2
Bit Devices Word devices Program Steps Type
OP X Y M S K H KnX KnY KnM KnS T C D E F
S *
n * * *
D *
LRC, LRCP: 7 steps
PULSE 16-bit 32-bit
ES2/EX2 SS2
SA2
SE
SX2 ES2/EX2 SS2
SA2
SE
SX2 ES2/EX2 SS2
SA2
SE
SX2
Operands:
S: Starting device for ASCII mode checksum n: Data length for LRC operation (n = K1~K256)
D: Starting device for storing the operation result
Explanations:
1. n: n must be an even number. If n is out of range, an error will occur and the instruction will not
be executed. At this time, M1067 and M1068 = ON and error code H’0E1A will be recorded in
D1067.
2. 16-bit mode: When LRC instruction operates with M1161 = OFF, hexadecimal data starting
from S is divided into high byte and low byte and the checksum operation is operated on n
number of bytes. After this, operation result will be stored in both hi-byte and low byte of D.
3. 8-bit mode: When LRC instruction operates with M1161 = ON, hexadecimal data starting from
S is divided into high byte (invalid) and low byte and the checksum operation is operated on n
number of low bytes. After this, operation result will be stored in low bytes of D (Consecutive 2
registers).
4. Flag: M1161 8/16-bit mode