Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Artm-831x
Table of contents
Document Outline
- ARTM-831X
- Contents
- About this Manual
- Introduction
- Hardware Preparation and Installation
- Controls, LEDs, and Connectors
- Functional Description
- 4.1 Block Diagram
- 4.2 ARTM-831X Base Unit
- 4.3 E1/T1 Mezzanine Expansion Unit
- 4.4 DS3/OC3 Mezzanine Expansion Unit
- Module Management Controller
- FRU Information and SDR Summary
- Sensor Data Records
- Base ARTM FPGA
- 8.1 Base ARTM Architectural Overview
- 8.2 Signals
- 8.2.1 Global Signals
- 8.2.2 RTM SPI Interface (Slave)
- 8.2.3 Mezzanine SPI Interface (Slave)
- 8.2.4 Mezzanine TSI Telecom clocks
- 8.2.5 MMC I2C Interface (Slave)
- 8.2.6 I2C Interfaces to Sonet SFP and 10GE SFP+
- 8.2.7 Telecom Base Clock Receive Clocks
- 8.2.8 Telecom Clocks
- 8.2.9 Status Sonet SFP
- 8.2.10 Control Sonet SFP
- 8.2.11 10GE Status/Control Signals
- 8.2.12 GE Control Signals
- 8.2.13 Ethernet Clock Signals
- 8.2.14 BITS 1 Signals
- 8.2.15 BITS 2 Signals
- 8.2.16 Identification Signals
- 8.2.17 Debug LEDs
- 8.2.18 Spare Signals
- 8.2.19 Configuration Signals
- 8.3 Registers
- 8.3.1 ARTM Base FPGA Register Overview
- 8.3.1.1 ARTM Base FPGA Code Main-Version
- 8.3.1.2 SFP I2C select Register
- 8.3.1.3 ARTM Base FPGA Code Sub-Version
- 8.3.1.4 SFP TXFAULT Status
- 8.3.1.5 SFP MOD_ABS Status
- 8.3.1.6 SFP TXDIS Control
- 8.3.1.7 10 GE Status Register
- 8.3.1.8 10 GE Control Register
- 8.3.1.9 MMC Scratch Register
- 8.3.1.10 RTM Scratch Register
- 8.3.1.11 Telecom Reference Clock Selection
- 8.3.1.12 GE Control Register
- 8.3.1.13 Force CRC Error Register
- 8.3.1.14 Test Register
- 8.3.1.15 Other Status Signals
- 8.3.1.16 SFP TXFAULT Level Changed
- 8.3.1.17 SFP TXFAULT interrupt enable
- 8.3.1.18 SFP MOD_ABS changed
- 8.3.1.19 SFP MOD_ABS interrupt enable
- 8.3.1.20 10 GE Status changed
- 8.3.1.21 10 GE Status interrupt enable
- 8.3.1.22 Telecom Reference Clock Divider Registers
- 8.3.1.23 ARTM Interrupt Group Status
- 8.3.1.24 Identification Register
- 8.3.1.25 FPGA Code SPI Update Registers
- 8.3.1.26 ARTM Telecom Clock Monitor Registers
- 8.3.1.27 ARTM Ethernet Reset Control Register
- 8.3.1 ARTM Base FPGA Register Overview
- 8.4 Reset Structure
- 8.5 Clocking Scheme
- 8.6 Logic Blocks
- TSI FPGA
- 9.1 Architectural Overview
- 9.2 Device Specifics
- 9.3 TSI FPGA Signals Overview
- 9.4 Logic Blocks
- 9.4.1 TSI - Time Slot Interchanger
- 9.4.2 GR8
- 9.4.3 Testpattern Generator (input)
- 9.4.4 Testpattern Comparator (input)
- 9.4.5 Testpattern Generator (output)
- 9.4.6 Testpattern Generator (output)
- 9.4.7 Frame Start Pulse Generator
- 9.4.8 PCIexpress Interface
- 9.4.9 Local Bus Master Interface
- 9.4.10 SPI Control Interface in Master Mode
- 9.4.11 SPI Expander Interface
- 9.4.12 Interrupt Controller
- 9.4.13 Debug LEDs
- 9.5 RTM FPGA HW/SW Interfaces
- 9.5.1 RTM FPGA Address map Overview
- 9.5.2 RTM FPGA Memories and Registers Detailed
- 9.5.2.1 TSI Memory (TsiMem)
- 9.5.2.2 GR8 Memory (Gr8Mem)
- 9.5.2.3 SerDes Client Interface (SerDesClientIf)
- 9.5.2.4 TSI Registers (TsiRegs)
- 9.5.2.5 Gr8 Registers (Gr8Regs)
- 9.5.2.6 TSI Interior/Exterior Test Pattern Generator Block (TsiTstPatGenBlk)
- 9.5.2.7 TSI Interior/Exterior Test Pattern Comparator Block (TsiTstPatCmpBlk)
- 9.5.2.8 Tsi to Serdes Converter Block (Tsi2SerBlk)
- 9.5.2.9 Deserializer to TSI Allocater Block (Des2TsiBlk)
- 9.5.2.10 Transport Overhead Registers (TohRegs)
- 9.5.2.11 General Register (GnrlRegs)
- 9.5.2.12 General Test Registers (GenTestRegs)
- 9.5.2.13 Framer and Line Interface Unit Sideband Signal Registers (FrLiuSdBndRegs)
- 9.5.2.14 Configuration Prom Update Registers accessed through RTM FPGA as bridge to SPI bus 0 (CfgPrmUpd)
- 9.5.2.15 External components accessed through RTM FPGA as bridge to SPI bus 1 (ExtBridgedCompSpi1)
- 9.5.2.16 External components accessed through RTM FPGA as bridge to SPI bus 2 (ExtBridgedCompSpi2)
- 9.5.2.17 External components accessed through RTM FPGA as bridge to SPI bus 3 (ExtBridgedCompSpi3)
- 9.5.2.18 External components accesses through RTM FPGA as bridge to local bus (ExtBridgedComp)
- 9.5.3 PCI Configuration Space
- 9.6 TSI channel mapping
- EXT FPGA
- A Related Documentation
- Safety Notes
- Sicherheitshinweise