9 mmc scratch register, 10 rtm scratch register, 11 telecom reference clock selection – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 136: Table 8-33, Mmc scratch register, Table 8-34, Rtm scratch register, Base artm fpga
Base ARTM FPGA
ARTM-831X Installation and Use (6806800M76E)
136
8.3.1.9
MMC Scratch Register
8.3.1.10 RTM Scratch Register
8.3.1.11 Telecom Reference Clock Selection
Select the source clock for the reference clocks CLK_REFCLK_1 and CLK_REFCLK_2.
With the Telecom Reference Clock Divider Registers, software can divide the selected
reference clock. See
Chapter 8, Telecom Reference Clock Divider Registers, on page 144
for details.
Table 8-33 MMC Scratch Register
Address: 0x9
Bit Description
Default
Access
7:0
MMC Scratch Register
PWR_GOOD: 0
MMC: r/w
RTM: r
Table 8-34 RTM Scratch Register
Address: 0xA
Bit Description
Default
Access
7:0
RTM Scratch Register
PWR_GOOD: 0
RTM: r/w
MMC: r
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