Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 274)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 274
9.5.2.13.4 Pmc83 and Xrt86 Framer Line Event Status Mask Register
Address:
0x1618, Pmc83Xrt86LineEvtMaskReg
Width: 32 bit
6 Xrt86Chp0RcvLoSReset6 RW 0b1:
Xrt86Chp0RcvLoSReset6,
resets chip 0 receiver Line 6
loss of signal indicator bit 0b0 X X
5 Xrt86Chp0RcvLoSReset5 RW 0b1:
Xrt86Chp0RcvLoSReset5,
resets chip 0 receiver Line 5
loss of signal indicator bit 0b0 X X
4 Xrt86Chp0RcvLoSReset4 RW 0b1:
Xrt86Chp0RcvLoSReset4,
resets chip 0 receiver Line 4
loss of signal indicator bit 0b0 X X
3 Xrt86Chp0RcvLoSReset3 RW 0b1:
Xrt86Chp0RcvLoSReset3,
resets chip 0 receiver Line 3
loss of signal indicator bit 0b0 X X
2 Xrt86Chp0RcvLoSReset2 RW 0b1:
Xrt86Chp0RcvLoSReset2,
resets chip 0 receiver Line 2
loss of signal indicator bit 0b0 X X
1 Xrt86Chp0RcvLoSReset1 RW 0b1:
Xrt86Chp0RcvLoSReset1,
resets chip 0 receiver Line 1
loss of signal indicator bit 0b0 X X
0 Xrt86Chp0RcvLoSReset0 RW 0b1:
Xrt86Chp0RcvLoSReset0,
resets chip 0 receiver Line 0
loss of signal indicator bit 0b0 X X
Bit Acronym Type Description Default Pwr Soft