Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 299)

EXT FPGA
ARTM-831X Installation and Use (6806800M76E) 299
0x84 UnOccpdAddrMonAddrRe
g Unoccupied Address Access Monitor Address Register
(32bit) [Hw: syn, WAck1, RAck1]
This register stores the address of the last access to an
unoccupied address area
Configuration Prom Update Registers (CfgPrmUpd) [Hw: Cy]
Allows to update the serial configuration prom of the FPGA
Access via Spi-bus 256Byte memory area, hereof assigned to this block: 90...9F
Address Acronym Description
0x90 CfgPrmUpdCtrReg Configuration Prom Update Control Register (8bit) [Hw:
syn, WAck5, RAck5, WRP]
Controls the update of the FPGA serial configuration prom
by the host processor via SPI bus.
0x91 CfgPrmUpdDatReg Configuration Prom Update Data Register (8bit) [Hw: syn,
WAck25, RAck25, WRP]
Holds the write data to sent to the FPGA serial
configuration prom when written and the read data
received from the FPGA serial configuration prom when
read.
General Test Registers (GenTestRegs) [Hw: Cy]
General Test Registers
Access via Spi-bus 256Byte memory area, hereof assigned to this block: A0...BF
Address Acronym Description
0xA0 FltInsrtReg Fault Insertion Register (32bit) [Hw: syn, WAck1, RAck1,
WTP]
Allows to simulate several faults initiated not by the original
source but by the host SW for test purposes
0xA4 ScratchPadReg ScratchPad Register (32bit) [Hw: syn, WAck1, RAck1]
Registermemory without any control or status function
0xA8 TestModeCtrlReg Test Mode Control Register (8bit) [Hw: syn, WAck1, RAck1]
Register to control testmodes
0xAC TestReadValReg Test Read Val Register (32bit) [Hw: syn, WAck1, RAck1]
Register to read data for Hw test purposes
Table 10-4 EXT FPGA Addressmap Overview (continued)