Tsi fpga, 16component event status mask register – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 249
TSI FPGA
ARTM-831X Installation and Use (6806800M76E)
249
9.5.2.11.16Component Event Status Mask Register
Address:
0x147C, CompEvtMaskReg
Width: 32 bit
5
Xrt86ChpIntrptReset3 RW
0b1: Xrt86ChpIntrptReset3,
resets CompEvtReg bit
IntrptXrt86_3
0b0
X
X
4
Xrt86ChpIntrptReset2 RW
0b1: Xrt86ChpIntrptReset2,
resets CompEvtReg bit
IntrptXrt86_2
0b0
X
X
3
Xrt86ChpIntrptReset1 RW
0b1: Xrt86ChpIntrptReset1,
resets CompEvtReg bit
IntrptXrt86_1
0b0
X
X
2
Xrt86ChpIntrptReset0 RW
0b1: Xrt86ChpIntrptReset0,
resets CompEvtReg bit
IntrptXrt86_0
0b0
X
X
1
Pmc83ChpIntrptReset
1
RW
0b1: Pmc83ChpIntrptReset1,
resets CompEvtReg bit
IntrptPmc83_1
0b0
X
X
0
Pmc83ChpIntrptReset
0
RW
0b1: Pmc83ChpIntrptReset0,
resets CompEvtReg bit
IntrptPmc83_0
0b0
X
X
Bit
Acronym
Type
Description
Default
Pwr
Soft
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