Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 315)

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ARTM-831X Installation and Use (6806800M76E) 315
23 Xrt86Chp4RcvLoSIntrpt
Mask7 RW 0b1:
Xrt86Chp4RcvLoSIntrptEnable7,
enables chip 4 receiver Line 7 loss
of signal interrupt bit 0b0 X X
22 Xrt86Chp4RcvLoSIntrpt
Mask6 RW 0b1:
Xrt86Chp4RcvLoSIntrptEnable6,
enables chip 4 receiver Line 6 loss
of signal interrupt bit 0b0 X X
21 Xrt86Chp4RcvLoSIntrpt
Mask5 RW 0b1:
Xrt86Chp4RcvLoSIntrptEnable5,
enables chip 4 receiver Line 5 loss
of signal interrupt bit 0b0 X X
20 Xrt86Chp4RcvLoSIntrpt
Mask4 RW 0b1:
Xrt86Chp4RcvLoSIntrptEnable4,
enables chip 4 receiver Line 4 loss
of signal interrupt bit 0b0 X X
19 Xrt86Chp4RcvLoSIntrpt
Mask3 RW 0b1:
Xrt86Chp4RcvLoSIntrptEnable3,
enables chip 4 receiver Line 3 loss
of signal interrupt bit 0b0 X X
18 Xrt86Chp4RcvLoSIntrpt
Mask2 RW 0b1:
Xrt86Chp4RcvLoSIntrptEnable2,
enables chip 4 receiver Line 2 loss
of signal interrupt bit 0b0 X X
17 Xrt86Chp4RcvLoSIntrpt
Mask1 RW 0b1:
Xrt86Chp4RcvLoSIntrptEnable1,
enables chip 4 receiver Line 1 loss
of signal interrupt bit 0b0 X X
16 Xrt86Chp4RcvLoSIntrpt
Mask0 RW 0b1:
Xrt86Chp4RcvLoSIntrptEnable0,
enables chip 4 receiver Line 0 loss
of signal interrupt bit 0b0 X X
15 Xrt86Chp3RcvLoSIntrpt
Mask7 RW 0b1:
Xrt86Chp3RcvLoSIntrptEnable7,
enables chip3 receiver Line 7 loss
of signal interrupt bit 0b0 X X
Bit Acronym Type Description Default Pwr Soft