Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 220)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 220
A Serdes reset or resync can be initiated via this register.
Reg0 is for Serdes-connection to the BaseBoard, Reg1 to DMC1 and Reg2 to DMC2.
9.5.2.9.2 Serdes Receiver Status Register
Addresses:
0x1201, SerDesRcvStatReg0
0x1241, SerDesRcvStatReg1
0x1281, SerDesRcvStatReg2
Width: 8 bit
Bit Acronym Type
Description
Default
Pwr Soft
7 SerdesRcvPllLolFlagR
eset RW 0b1: SerdesRcvPllLolFlagReset, resets
the loss of lock flag bit in
SerDesRcvStatReg 0b0 X X
6 SerdesRcvLosFlagRes
et RW 0b1: SerdesRcvLosFlagReset, resets the
loss of signal flag bit in
SerDesRcvStatReg 0b0 X X
5 SerdesRcvHasFound
CommaFlagReset RW 0b1:
SerdesRcvHasFoundCommaFlagReset,
resets the not found comma flag bit in
SerDesRcvStatReg 0b0 X X
4...
2 - - reserved undef - -
1 SerdesRcvResync RW 0b1: SerdesRcvResync, Serdes receiver
starts waiting for comma characters
again, a 1 to 0 transition starts waiting,
SerdesRcvHasFoundComma and
SerdesRcvHasFoundCommaFlag bits in
the serdes receiver status register show
the progress. 0b0 X X
0 SerdesRcvReset RW 0b1: SerdesRcvReset, puts the Serdes
receiver into reset, resync sequence is
sent automatically when deactivated 0b0 X X