Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 66)

Functional Description
ARTM-831X Installation and Use (6806800M76E) 66
4.2 ARTM-831X Base Unit
4.2.1 FPGA_base
The FPGA_base contains two functionalities. One section is responsible to support IP-only
functionality of an ARTM8310 and provides glue logic for the ARTM-831X_base PCA. The
other section provides additional support and glue logic for the optional TDM expansion
mezzanine PCA's.
Key Features of the IP section:
 Controlled via SPI from front board
 Controls the 10Gb SFP+ modules and collects the overhead signals
 Clock selector between IP and TDM recovered receive clock's (any 2 of available input
clocks are sent as a reference input clock to the eSETS PLL on the front board)
- configurable divider for selected receive clock
 Clock gate on LOS condition for IP recovered receive clocks
 Update/failback SPI configuration Flash in working/golden mode
Key Features of the TDM expansion section:
 Controlled from Host via SPI through the TSI-FPGA on a TDM expansion PCA
 SPI control to the BITS interface devices
 Controls the OC3/OC12 SFP modules and collects the overhead signals
 Clock selector among TDM sources such as the BITS recovered clock, TSI FPGA pre-
selected clock, and TSI Extender pre-selected clock
 Clock gate on LOS condition for BITS recovered clock
 Update/failback SPI configuration Flash in working/golden mode